library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity RAM is
	port(
        en : in std_logic; -- 0: disable, 1: enable
        rw : in std_logic; -- 0: read, 1: write
        reset : in std_logic; -- 0: no reset, 1: reset
		addr: in std_logic_vector(7 downto 0);
		data: inout std_logic_vector(7 downto 0)
	);
end RAM;
architecture my_ram_arch of RAM is
	type my_ram_type is array (0 to 15) of std_logic_vector(7 downto 0);
	signal my_ram: my_ram_type := (
        0 => X"01", -- 地址0的初始数据
        1 => X"02", -- 地址1的初始数据
        2 => X"03", -- 地址2的初始数据
        3 => X"04", -- 地址3的初始数据
        others => (others => '0')
    );
    -- 可以在此处预先写入数据
begin
	process(en, addr, data)
	begin
        if en = '1' then
            if reset = '1' then -- 重置操作
                -- 可以在此处写入初始化的数据
                my_ram <= (
                    0 => X"01", -- 地址0的初始数据
                    1 => X"02", -- 地址1的初始数据
                    2 => X"03", -- 地址2的初始数据
                    3 => X"04", -- 地址3的初始数据
                    others => (others => '0')
               );
            else
                if rw = '1' then -- 写操作
                    my_ram(to_integer(unsigned(addr))) <= data;
                else -- 读操作
                    data <= my_ram(to_integer(unsigned(addr)));
                end if;
            end if;
        else
            data <= (others => 'Z');
        end if;
    end process;
end my_ram_arch;
			